This application is based upon and claims priority of Japanese Patent Application No. 2001-71791, filed in Mar. 14, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
As one of the nonvolatile memory that can store the information after the power supply is turned off, there is known the FeRAM (Ferroelectric Random Access Memory) having the ferroelectric material. The FeRAM has the structure that can store the information by utilizing the hysteresis characteristic of the ferroelectric material, and permits the high speed operation, and has the low power consumption. Thus, the future development of the FeRAM is anticipated as the nonvolatile memory that permits the large number of times of the writing operation.
FIGS. 1A and 1B show an example of a circuit diagram of an FeRAM memory cell respectively.
FIG. 1A show an example of a circuit diagram of the type in which two transistors T11, T12 and two capacitors C11, C12 are employed to store one-bit information (referred to as a xe2x80x9c2T2C typexe2x80x9d hereinafter). The 2T2C type FeRAM memory cell executes an complementary operation to store xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d data into one capacitor and store the opposite data into the other capacitor. At the time of decision of the data, polarization states of both capacitors C11, C12 are read, and then the data decision is carried out by using difference between them.
FIG. 1B is a circuit diagram of the type in which one transistor To and one capacitor Co are employed to store one-bit information (referred to as a xe2x80x9c1T1C typexe2x80x9d hereinafter). The 1T1C type employs one transistor and one capacitor for one-bit information. Also, the 1T1C type needs the reference capacitor C1 that generates the reference voltage to decide that the charge read from the memory cell is the data of xe2x80x9c1xe2x80x9d or the data of xe2x80x9c0xe2x80x9d. The polarization of the reference capacitor C1 is inverted every time when the data is read out. The decision of data is executed based on the large or small relationship between the potential of the capacitor Co of each memory cell and the potential of the reference capacitor C1. The reference capacitor C1 is connected to an end portion of each bit line BIT. Ideally, it is desired that the potential of the reference capacitor C1 should be set to an intermediate potential between the voltage V1 at which xe2x80x9c1xe2x80x9d is written into the memory cell and the voltage V0 at which xe2x80x9c0xe2x80x9d is written into the memory cell.
The 1T1C type memory cell can reduce a cell area to almost half rather than the 2T2C type FeRAM memory cell. FIG. 2 shows a plan view of a structure in which the arrangement of the 2T2C type memory cell is applied to the 1T1C type memory cell.
In FIG. 2, a plurality of stripe-like capacitor lower electrodes 103 that extend in the Y direction are formed at an interval over a device isolation layer 102 on a semiconductor substrate 101 in the X direction. Then, ferroelectric films 104 each having the almost same shape as the capacitor lower electrode are formed on the capacitor lower electrodes 103. Then, a plurality of capacitor upper electrodes 105 are formed on the ferroelectric films 104 to be aligned in the Y direction. One capacitor Co consists of the capacitor upper electrode 105, the ferroelectric film 104, and the capacitor lower electrode 103.
Also, a pair of transistors To are formed in active regions, that are surrounded by the device isolation layer 102, on both sides of the capacitor upper electrode 105 on the semiconductor substrate 101. Then, a plurality of capacitor upper electrodes 105 formed on the capacitor lower electrodes 103 are connected sequentially to the transistor To on one side and the transistor To on other side alternatively.
Two transistors To are formed in one active region surrounded by the device isolation layer 102. Two gate electrodes 106 that are also used as word lines WL extending in the Y direction are formed in the active region via a gate insulating film (not shown). Impurity diffusion areas 107a, 107b, 107c are formed in the active regions on both sides of two gate electrodes 106.
Bit lines BIT connected to the impurity diffusion area 107b in the center of the active region are formed over the capacitor Co and the transistor To so as to extend in the X direction. Also, the impurity diffusion areas 107a, 107c on both ends of the active region are connected to the capacitor upper electrode 105 via a local-interconnection wiring 108 that is formed below the bit line BIT along the bit line BIT.
In FIG. 2, an interlayer insulating film formed on the semiconductor substrate 101 is omitted.
In FIG. 2, since a plurality of transistors To existing in the Y direction are connected to a plurality of capacitor upper electrodes 105 formed on the side of the transistor every other electrode respectively, a wide margin exists between the transistors To.
Therefore, as shown in FIG. 3, in order to place the capacitor Co in the area between the transistors To existing in the Y direction, it is set forth in Tatsuya Yamazaki et. al, xe2x80x9cAdvanced 0.5 xcexcm FEAM Device Technology with Full Compatibility of Half-Micron CMOS Logic Devicexe2x80x9d 1997 IEEE IEDM to form the capacitor upper electrodes 105 in a zigzag fashion. Accordingly, an interval between the transistors To in the X direction is narrowed.
FIG. 4A is a sectional view of the memory cell shown in FIG. 3 taken along a Ixe2x80x94I line, and FIG. 4B is a sectional view of the reference capacitor connected to the bit line BIT.
In FIG. 4A, the device isolation layer 102 and the transistor To on the semiconductor substrate 101 are covered with a first interlayer insulating film 111 and a second interlayer insulating film 112. Holes are formed in the first interlayer insulating film 111 on the impurity diffusion areas 107a, 107b, 107c respectively, and contact plugs 109a, 109b, 109c are buried in these holes respectively. The capacitors Co are formed on the second interlayer insulating film 112, and a third interlayer insulating film 113 is formed on the capacitors Co. Also, the local-interconnection wirings 108 are formed on the third interlayer insulating film 113. The local-interconnection wirings 108 are connected to the capacitor upper electrode 105 via a hole in the third interlayer insulating film 113 respectively, and also connected to the contact plugs 109a, 109c on the end portions of the active regions via another holes in the second and third interlayer insulating films 112, 113 respectively. Also, the bit line BIT is formed on a fourth interlayer insulating film 114 that covers the local-interconnection wirings 108. The bit line BIT is connected to the contact plug 109b in the center of the active region via a hole that is formed in the first, second, third and fourth interlayer insulating films 111, 112, 113, 114.
In FIG. 4B, a reference capacitor C1 consisting of a lower electrode 115, a ferroelectric film 116, and an upper electrode 117 is formed on the second interlayer insulating film 112 formed over the semiconductor substrate 101. The reference capacitor C1 is covered with the third interlayer insulating film 113. Also, a local-interconnection wiring 118 that is connected to the upper electrode 117 of the reference capacitor C1 via a hole is formed on the third interlayer insulating film 113. This local-interconnection wiring 118 is extended to the outside to pass over the upper electrode 117. Also, the bit line BIT connected to another reference capacitor is formed over the reference capacitor C1 via the fourth interlayer insulating film 114.
By the way, following problems exist in the structures shown in FIG. 3 and FIG. 4.
A first problem is that the parasitic capacitance that is constructed by the bit line BIT and the underlying local-interconnection wiring 108 in the memory cell disturbs the higher speed operation of the FeRAM.
A second problem is that the resist coated on the peripheral portion of the FeRAM chip is ready to thin. For example, as shown in FIG. 5A, if a resist 120 is coated on the fourth interlayer insulating film 114 that covers the reference capacitor Co, there is such a tendency that the resist 120 become thin in the neighborhood 120a of the deeply stepped portion of the reference capacitor Co. If the etching is carried out in such state, the resist 120 is etched to expose a part of the fourth interlayer insulating film 114 and subsequently a part of the fourth interlayer insulating film 114 is etched to expose a part of the leading electrode 118, as shown in FIG. 5B. If the bit line BIT shown in FIG. 4B is formed in this state, there is caused the problem that the short-circuit between the bit line BIT and the leading electrode 118 is caused at the location where they are not essentially connected.
In this case, if the fourth interlayer insulating film 114 is formed thick and then the fourth interlayer insulating film 114 is planarized by the chemical mechanical polishing (CMP) method, the situation that a thickness in the resist 120 is reduced in the peripheral area of the chip can be prevented. However, since the cost-up has already been brought about in the FeRAM by using the noble metal as the capacitor lower electrode 103, etc., it is not preferable to employ the CMP that causes the higher cost.
It is an object of the present invention to provide a semiconductor device capable of increasing its operation speed higher than the prior art and also preventing the reduction in thickness of resist in a peripheral area of a chip, and a method of manufacturing the same.
According to the present invention, the switching element (transistors) and the capacitor are connected by the first wirings (local-interconnection wirings) that extend in the first direction, and the second wirings (bit lines), that are formed over the switching element and the capacitor, are extended in the second direction that intersects with the first direction.
Therefore, since the extended directions of the first wirings and the second wirings intersect with each other, the opposing area between the first wiring and the second wiring can be reduced rather than the prior art, and also the capacitance formed by the first wiring and the second wiring can be reduced rather than the prior art. As a result, the higher speed operation of the semiconductor device can be attained.
Also, in case a plurality of capacitors exist over and around the switching element and also the wirings are formed over the switching elements by forming the metal film over the switching elements and the capacitors and then patterning this metal film while using the resist, the exposure light that is reflected by the inclined surface of the metal film around the capacitors causes the halation to cause the reduction in width of the resist pattern.
In this case, since the resist coated over the capacitor and the switching element is patterned at the level difference portion of the capacitor not to irradiate the exposure light, the wiring-forming resist pattern over the switching element is extended up to the level difference portion of the capacitor. Therefore, since the halation due to the level difference is hard to occur, the reduction in thickness of the resist pattern can be eliminated and thus the generation of the wiring failure can be prevented.
In addition, according to the present invention, the wiring connected to the upper electrode of the reference capacitor, that is formed in the chip peripheral portion of the semiconductor memory device, is extended to the outside of the reference capacitance in the area where the resist tends to become thin.
Therefore, the level difference under the resist is relaxed to be smooth above the reference capacitor and the outskirts of its, and thus the thinning of the resist caused by the level difference of the reference capacitor is suppressed. As a result, when the insulating film is etched and patterned by using the resist pattern, the situation that the insulating film covered with the resist pattern in the chip peripheral portions are exposed by the etching can be eliminated and in turn the exposure of the wirings under the resist pattern can be prevented.